发明名称 Monolithic three-dimensional semiconductor device and structure
摘要 A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.
申请公布号 US8754533(B2) 申请公布日期 2014.06.17
申请号 US201012949617 申请日期 2010.11.18
申请人 Monolithic 3D Inc. 发明人 Or-Bach Zvi;Cronquist Brian;Beinglass Israel;de Jong Jan Lodewijk;Sekar Deepak C.
分类号 H01L29/40;H01L23/544;H01L27/02;H01L27/115;H01L27/12;H01L29/66;H01L21/822;H01L27/108;H01L27/112;H01L27/11;H01L27/105;H01L27/06;H01L27/118;H01L21/762;H01L21/84;H01L23/48;H01L29/78 主分类号 H01L29/40
代理机构 Tran & Associates 代理人 Tran & Associates
主权项 1. A semiconductor device comprising: a first monocrystalline layer comprising first transistors and first alignment marks, and a first metal layer forming at least a portion of connections between said first transistors; and a second layer comprising second transistors, said second transistors consisting essentially of monocrystalline material, said second layer overlying said first metal layer, wherein said first metal layer comprises aluminum or copper,wherein said second layer is less than 1 micron in thickness and the first alignment marks are detectable through the second layer and the second layer comprises logic cells, andwherein said second transistors are aligned to at least one of said first alignment marks with less than 40 nm alignment error.
地址 San Jose CA US