Frequency synthesis methods and systems

摘要

Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a first phase locked loop (PLL), which may include an inductive-capacitive voltage-controlled oscillator (LC VCO). One or more subsequent tiers may each include a second PLL, which may include a self-biased (SB) VCO PLL or a digitally-controlled oscillator (DCO) PPL. A subsequent tier may be controllable with respect to multiple parameters. Parameters may be evaluated and selected based on multiple criteria, which may be prioritized. Parameters may be selected, for example, to minimize a frequency error equal relative to a permissible deviation from a desired frequency as a first priority, reduce jitter as a second priority, and minimize a frequency error relative to the desired frequency as a third priority.

主权项

1. A system, comprising:
a first circuit portion, including a first phase locked loop (PLL), to generate a substantially fixed-frequency first interim clock from an input reference clock; and a second circuit portion, including a second PLL, to generate a first output clock from the first interim clock, wherein the second circuit portion is configurable with respect to multiple parameters to generate the first output clock at one of multiple selectable frequencies; and a control portion to select parameter values to apply to the second circuit portion, including to,
identify parameter values for which a frequency difference between the first output clock and a desired frequency is equal to or less than a threshold value, as a first priority,identify parameter values for which first output clock jitter is lowest, as a second priority, andidentify parameter values for which the frequency difference between the first output clock and the desired frequency is lowest, as a third priority.