Microprocessor having a low-power mode and a non-low power mode, data processing system and computer program product

摘要

A microprocessor has a low-power mode and a non-low power mode. The microprocessor includes a processor core for executing instructions provided to the microprocessor and a clock providing a clock signal, which in the non-low power mode has a first frequency and in the low power mode has a second frequency lower than the first frequency. A hardware timer is present, for scheduling an execution of an event by the microprocessor at a future point in time. The hardware timer is connected to the clock for determining a period of time between a current point in time and a point in time the event based on a number of clock cycles of the clock signal. A timer controller can determine, when the data processing system switches from the low power mode to the non-low power mode, a number of clock cycles of a clock signal with the first frequency that corresponds to a low-power mode period during which the microprocessor has been in the low power mode and adjusting the hardware timer based on the determined number.

主权项

1. A microprocessor having a low power mode and a non-low power mode, said microprocessor comprising:
a processor core for executing instructions provided to said microprocessor; a clock driver for a clock providing a clock signal which in said non-low power mode has a first frequency and in said low power mode has a second frequency lower than said first frequency; a hardware timer connected to the clock driver, the hardware timer for scheduling an execution of an event by said microprocessor at a future point in time, and to store a first counter value representing a remaining period of time between a current point in time and the future point in time as a number of clock cycles of said clock signal at the first frequency; and a timer controller for storing, in response to said microprocessor switching from said non-low power mode to said low power mode after the hardware timer is started, a second counter value that is a second number of clock cycles at the first frequency from a start point to the current point of time, calculating, in response to said microprocessor switching from said non-low power mode to said low power mode after the hardware timer is started, a third counter value based on the first and second counter values, the third counter value is a number of clock cycles of the clock signal at said second frequency that corresponds to the remaining period of time represented by the number of clock cycles of the clock signal at the first frequency, and storing the third counter value to represent the remaining period of time between the current point of time and the future point in time as the number of clock cycles of the clock signal at the second frequency, wherein the hardware timer is set to expire at the future point in time in response to the third counter value of the hardware timer.