Fault detection method of semiconductor manufacturing processes and system architecture thereof

摘要

A fault detection method of semiconductor manufacturing processes is disclosed. The method includes the steps of providing a storage device, collecting a fault detection and classification(FDC) parameter by the storage device, setting up a measurement site for measuring an online measurement parameter, collecting a wafer acceptance test(WAT) in correspondence to the FDC parameter, establishing a first relationship equation between the FDC parameter and the online measurement parameter, establishing a second relationship equation of the online measurement parameter and the WAT by using the first relationship equation, establishing a third relationship equation between the FDC parameter and the WAT, establishing a waning region of the manufacturing processes by using the first, second, and third relationship equations, and determining the situation of generating wafer defects according to the warning region. The present invention discloses a system architecture for the method.

主权项

1. A system architecture for executing a fault detection method of semiconductor manufacturing processes, comprising:
at least one storage unit having a storage device which is configured to store a plurality of fault detection and classification parameters, online measurement parameters, and wafer acceptance test parameters, wherein the fault detection and classification parameters and the online measurement parameters are defined as a first data group, and the wafer acceptance test parameters are defined as a second data group; an automation data analysis device including: a group analysis unit data linked to the storage device, configured to set up the fault detection and classification parameters and the online measurement parameters to establish a first relationship equation; a risk assessment unit data linked to the group analysis unit, configured to accept the wafer acceptance test parameters in such a way that the group analysis unit is further configured to establish a second relationship equation based on the online measurement parameters and the wafer acceptance test parameters according to the first relationship equation and a third relationship equation based on the fault detection and classification parameters and the wafer acceptance test parameters; a defect location unit data linked to the group analysis, configured to establish a curve distribution diagram based on the fault detection and classification parameters and the online measurement parameters; a range establishment unit data linked to the risk assessment unit, configured to establish a warning region according to the first, second, and third relationship equations; and a risk determination unit data linked to the defect location unit and the range establishment unit, configured to evaluate a defect generation condition of the semiconductor manufacturing processes by the warning region; an image display device data linked to the risk determination unit for displaying the defect generation condition of the semiconductor manufacturing processes.