Methods for designing semiconductor device with dynamic array section

摘要

A method is provided for designing an integrated circuit device. The method includes placing four transistors of a first transistor type and four transistors of a second transistor type within a gate electrode level. Each of the transistors includes a respective linear-shaped gate electrode segment positioned to extend lengthwise in a first direction. The transistors of the first and second transistor types are placed according to a substantially equal centerline-to-centerline spacing as measured perpendicular to the first direction. A first linear conductive segment is placed to electrically connect the gate electrodes of the first transistors of the first and second transistor types. A second linear conductive segment is placed to electrically connect the gate electrodes of the fourth transistors of the first and second transistor types. A third linear conductive segment is placed beside either the first or second linear conductive segment.

主权项

1. A method for designing an integrated circuit device, comprising:
performing one or more operations, using a computer, to place a first transistor of a first transistor type within a gate electrode level layout; performing one or more operations, using the computer, to place a second transistor of the first transistor type within the gate electrode level layout; performing one or more operations, using the computer, to place a third transistor of the first transistor type within the gate electrode level layout; performing one or more operations using the computer, to place a fourth transistor of the first transistor type within the gate electrode level layout, wherein each of the first, second, third, and fourth transistors of the first transistor type includes a respective linear-shaped gate electrode segment positioned to extend lengthwise in a first direction, and wherein the first, second, third, and fourth transistors of the first transistor type are placed according to a substantially equal centerline-to-centerline spacing as measured perpendicular to the first direction between centerlines of adjacently placed linear-shaped gate electrode segments; performing one or more operations, using the computer, to place a first transistor of a second transistor type within the gate electrode level layout; performing one or more operations, using the computer, to place a second transistor of the second transistor type within the gate electrode level layout; performing one or more operations, using the computer, to place a third transistor of the second transistor type within the gate electrode level layout; performing one or more operations, using the computer, to place a fourth transistor of the second transistor type within the gate electrode level layout, wherein each of the first, second, third, and fourth transistors of the second transistor type includes a respective linear-shaped gate electrode segment positioned to extend lengthwise in the first direction, and wherein the first, second, third, and fourth transistors of the second transistor type are placed according to the substantially equal centerline-to-centerline spacing as measured perpendicular to the first direction; performing one or more operations, using the computer, to place a first linear conductive segment within the gate electrode level layout to electrically connect the gate electrode of the first transistor of the first transistor type to the gate electrode of the first transistor of the second transistor type; performing one or more operations, using the computer, to place a second linear conductive segment within the gate electrode level layout to electrically connect the gate electrode of the fourth transistor of the first transistor type to the gate electrode of the fourth transistor of the second transistor type; and performing one or more operations, using the computer, to place a third linear conductive segment within the gate electrode level layout beside either the first linear conductive segment or the second linear conductive segment according to the substantially equal centerline-to-centerline spacing as measured perpendicular to the first direction, wherein the first, second, and third linear conductive segments extend in the first direction parallel to each other.