Delay control circuit and clock generation circuit including the same

摘要

A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information.

主权项

1. A clock generation circuit comprising:
a delay line configured to delay an input clock and generate a delayed clock; a delay modeling unit configured to delay the delayed clock by a modeled delay value and generate a feedback clock; a phase detection unit configured to compare phases of the input clock and the feedback clock and generate a phase detection signal; a filter unit configured to receive the phase detection signal and generate phase information, generate an update signal when a difference between the number of phase detection signals with a first level generated and the number of phase detection signals with a second level generated is greater than or equal to a threshold value, and generate the update signal after a lapse of a predetermined time when the difference is less than the threshold value; and a delay line control unit configured to set a delay value of the delay line in response to the update signal and the phase information.