Asymmetric silicon-on-insulator SRAM cell

摘要

A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric.

主权项

1. A method of making a memory cell comprising:
forming a pair of access transistors over a first region of a semiconductor substrate, the first region being at least one of an n-type and a p-type dopant; forming a pair of pull-down transistors over the first region; forming a pair of pull-up transistors over a second region of the semiconductor substrate, the second region being at least one of the n-type and p-type dopant; coupling the pair of pull-down transistors and the pair of pull-up transistors between the pair of access transistors to form a memory cell; performing a single sided halo implant on at least one of the pair of the pull-down transistors and the pair of the pull-up transistors, the single sided halo implant providing asymmetry to the memory cell; and performing a dual-sided halo implant on the access transistors, the duel-sided halo implant providing symmetry to the memory cell.