| 发明名称 | Memory address translation | ||
| 摘要 | The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address. | ||
| 申请公布号 | US8756400(B2) | 申请公布日期 | 2014.06.17 |
| 申请号 | US201313859502 | 申请日期 | 2013.04.09 |
| 申请人 | Micron Technology, Inc. | 发明人 | Manning Troy A.;Culley Martin L.;Larsen Troy D. |
| 分类号 | G06F12/00 | 主分类号 | G06F12/00 |
| 代理机构 | Brooks, Cameron & Huebsch, PLLC | 代理人 | Brooks, Cameron & Huebsch, PLLC |
| 主权项 | 1. A memory device, comprising: a memory array including a first table having a number of records, wherein: each of the number of records includes a number of entries; andeach of the number of entries in each of the number of records includes a physical address corresponding to a data segment stored in the array and a logical address; and a controller coupled to the array and including a second table having a number of records, wherein: each of the number of records includes a number of entries; andeach of the number of entries in each of the number of records includes a physical address corresponding to a record in the first table and a logical address. | ||
| 地址 | Boise ID US | ||