| 发明名称 |
MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME |
| 摘要 |
A memory controller includes a register configured to store a parity check matrix, and an error correcting code (ECC) decoder configured to perform error bit correction on data supplied from a non-volatile memory device using the parity check matrix. The parity check matrix includes N column matrices, where N is a natural number. Each of the N column matrices includes multiple sub-matrices, and a last sub-matrix of the multiple sub-matrices of each column matrix, which is a non-zero valued matrix that comes last in an decoding sequence of the ECC decoder, is an identity matrix. |
| 申请公布号 |
US2014164875(A1) |
申请公布日期 |
2014.06.12 |
| 申请号 |
US201314079659 |
申请日期 |
2013.11.14 |
| 申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM SANG-MIN;KONG JUN-JIN |
| 分类号 |
G06F11/10 |
主分类号 |
G06F11/10 |
| 代理机构 |
|
代理人 |
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| 主权项 |
1. A memory controller, comprising:
a register configured to store a parity check matrix; and an error correcting code (ECC) decoder configured to perform error bit correction on data supplied from a non-volatile memory device using the parity check matrix, the parity check matrix including N column matrices, where N is a natural number, wherein each of the N column matrices comprises a plurality of sub-matrices, and a last sub-matrix of the plurality of sub-matrices of each column matrix, which is a non-zero valued matrix that comes last in an decoding sequence of the ECC decoder, is an identity matrix.
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| 地址 |
SUWON-SI KR |
