SEMICONDUCTOR MEMORY DEVICE

摘要

A semiconductor memory device includes a memory cell array, a plurality of reference cell arrays, a plurality of word lines, a plurality of bit lines, a plurality of reference word lines, a plurality of reference bit lines each being provided for an associated one of the reference cell arrays, and equalizing transistors each of which is provided between the plurality of reference bit lines and receives an associated one of independent control signals, and a potential of one of the plurality of reference bit lines and a plurality of one of the plurality of bit lines are input to a sense amplifier.

主权项

1. A semiconductor memory device, comprising:
a memory cell array including a plurality of memory cells which are arranged in a matrix and each include a resistance chancing element; a plurality of reference cell arrays each including a plurality of reference cells which are arranged in a matrix and each include a resistance changing element, the plurality of reference cell arrays being arranged in line in a row direction of the memory cell array; a plurality of word lines each being provided for an associated one of rows of the memory cell array and commonly connected to multiple ones of the plurality of memory cells arranged in the associated row; a plurality of bit lines each being provided for an associated one of columns of the memory cell array and commonly connected to multiple ones of the plurality of memory cells arranged in the associated column; a plurality of reference word lines each being provided for an associated one of rows of the plurality of reference cell arrays and commonly connected to multiple ones of the plurality of reference cells arranged in the associated one of the rows of the plurality of reference cell arrays; a plurality of reference bit lines each being provided for an associated one of the plurality of reference cell arrays so as to extend in a column direction and commonly connected to multiple ones of the plurality of reference cells included in the associated reference cell array; and a plurality of equalizing transistors each being provided between the plurality of reference bit lines and configured to receive an associated one of independent control signals supplied to a gate thereof,wherein
a potential of one of the plurality of reference bit lines and a potential of one of the plurality of bit lines are input to a sense amplifier.