| 摘要 |
PROBLEM TO BE SOLVED: To correctly detect a signal delay when a failure occurs in an exclusive OR circuit itself that constitutes a signal delay detection circuit.SOLUTION: A malfunction predetection circuit 12 includes: a delay circuit DL that delays input data to a data input terminal of an FF1 that is provided in a stage subsequent to an FF0; an FFT that receives the output of the delay circuit DL; and a comparator CMP that performs comparison between the output of the FF1 and the output of the FFT. In an operation test of the malfunction predetection circuit 12, test data tv1 and test data tv2 are input to the malfunction predetection circuit 12. The test data tv2 is input to the delay circuit DL. In the operation test, the comparator CMP performs comparison between the test data tv1 and the output of the FFT. |
