PHYSICS-BASED RELIABILITY MODEL FOR LARGE-SCALE CMOS CIRCUIT DESIGN

摘要

This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.

主权项

1. A method of simulating a physical active semiconductor component using an in silico active semiconductor component configured to operationally simulate the physical active semiconductor component, comprising:
generating a simulated input signal having a simulated input signal level; producing a simulated defect signal level, wherein the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and the simulated input signal level of the simulated input signal; adjusting the simulated input signal level of the simulated input signal in accordance with the simulated defect signal level; and implementing the in silico active semiconductor component so as to generate a simulated output signal in response to the simulated input signal after the simulated signal level of the simulated input signal is adjusted in accordance with the simulated defect signal level.