DATA INTERFACE CLOCK GENERATION

摘要

In one embodiment, an apparatus may include a clock generator to generate a first clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the first clock signal and the serial data.

主权项

1. An apparatus comprising:
a clock generator to generate a first clock signal based on a gear selection input; a serializer to receive parallel input data and generate serial data from the parallel input data; and a signal generator to generate a differential signal pair based on the first clock signal and the serial data, the differential signal pair to communicate pulse width modulated (PWM) data.