ACTIVE DEVICE ARRAY SUBSTRATE AND DISPLAY PANEL

摘要

An active device array substrate and a display panel are provided. The active device array substrate includes a substrate, a first conductor layer, a gate dielectric layer, a second conductor layer, an overcoat layer, a transparent electrode, a capacitive layer and pixel electrodes. The first conductor layer includes gate lines and light-shielding patterns. The gate dielectric layer covers the first conductor layer. The second conductor layer includes data lines and drain electrodes. Each of the data lines correspondingly overlaps one of the light-shielding patterns. The transparent electrode covers the overcoat layer. The pixel electrode is disposed on the capacitive layer and covers a portion of the shielding pattern. Each of the light-shielding patterns has a width greater than that of the overlapping data line. The gap between the edge of the light-shielding pattern and that of the overlapping data line is not greater than 2.5 microns.

主权项

1. An active device array substrate, comprising:
a substrate; a first conductor layer disposed on the substrate and comprising a plurality of gate lines and a plurality of light-shielding patterns; a gate dielectric layer covering the first conductor layer; a second conductor layer disposed on the gate dielectric layer and comprising a plurality of data lines and a plurality of drain electrodes, wherein each of the data lines correspondingly overlaps one of the light-shielding patterns, and the data lines and the gate lines intersect with each other to define a plurality of sub-pixel areas of the substrate; an overcoat layer covering the second conductor layer and the sub-pixel areas of the substrate; is a transparent electrode covering the overcoat layer, wherein the transparent electrode has a common voltage potential; a capacitive layer covering the transparent electrode; and a plurality of pixel electrodes disposed on the capacitive layer and covering the sub-pixel areas of the substrate and a portion of the light-shielding patterns, wherein the pixel electrodes are respectively connected to the drain electrodes, wherein each of the light-shielding patterns has a width greater than the width of the overlapping data line, and a gap between the edge of each of the light-shielding patterns and the edge of the overlapping data line is less than or equal to 2.5 microns.