HIGH-PERFORMANCE ECC DECODER

摘要

Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

主权项

1. An memory controller, comprising:
an Error Correction Code (ECC) unit configured to:
receive data from a memory, wherein the data is encoded with an ECC, and includes at least one code word;calculate a syndrome for the at least one code word;calculate an Error Locator Polynomial (ELP) dependent upon the calculated syndrome; andmodify a frequency of a clock signal dependent upon an actual number of errors in the at least one code word; and a processing unit coupled to the ECC unit, wherein the processing unit is configured to:
receive the clock signal; anddetermine roots of the ELP.