| 摘要 |
Provided is a delay locked loop (DLL) circuit whose operation delay amount is to be effectively used, comprising a first DLL variably delaying a first internal clock corresponding to a first edge of a source clock and outputting a first delay locked clock to make delay locking, a second DLL variably delaying a second internal clock corresponding to a second edge of the source clock and outputting a second delay locked clock to make delay locking, and a clock input multiplexing unit initializing the first DLL in response to activation of an input control signal indicating that the first and second DLLs fail to make delay locking, and subsequently inputting the second delay locking clock, instead of the first internal clock, to the first DLL. |
