VIRTUAL ADDRESS CACHE MEMORY, PROCESSOR AND MULTIPROCESSOR

摘要

An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.

主权项

1. A processor comprising:
a CPU; a primary cache memory; and a secondary, tertiary or more-order cache memory, wherein the secondary or tertiary or more-order cache memory comprises:
a TLB virtual page memory configured to hold entry data comprising a virtual page tag, the virtual page tag being a predetermined high-order bit (most significant bit side) of a virtual address for a process, and to output a hit signal when the virtual page tag corresponds to a virtual page tag from a processor;a data memory configured to hold cache data using the virtual page tag or a page offset as a cache index; anda cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index.