ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME

摘要

An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads.

主权项

1. An interconnect assembly for an embedded chip package, the interconnect assembly comprising:
an insulating substrate; a first metal layer comprising a plurality of upper contact pads, wherein a first surface of the plurality of upper contact pads is affixed to a top surface of the insulating substrate; a second metal layer comprising a plurality of lower contact pads, wherein a first surface of the plurality of lower contact pads is affixed to a bottom surface of the insulating substrate; and a plurality of electrical connections formed through the insulating substrate and in electrical contact with the plurality of upper contact pads and the plurality of lower contact pads, wherein a portion of a bottom surface of the plurality of electrical connections is directly coupled to the top surface of the insulating substrate.