发明名称 EXECUTION EFFICIENCY IN A SINGLE-PROGRAM, MULTIPLE-DATA PROCESSOR
摘要 A method for executing instructions on a single-program, multiple-data processor system having a fixed number of execution lanes, including: scheduling a primary instruction for execution with a first wave of multiple data; assigning the first wave to a corresponding primary subset of the execution lanes; scheduling a secondary instruction having a second wave of multiple data, such that the second wave fits in lanes that are unused by the primary subset of lanes; assigning the second wave to a corresponding secondary subset of the lanes; fetching the primary and secondary instructions; configuring the execution lanes such that the primary subset is responsive to the primary instruction and the secondary subset is simultaneously responsive to the secondary instruction; and simultaneously executing the primary and secondary instructions in the execution lanes.
申请公布号 US2014164737(A1) 申请公布日期 2014.06.12
申请号 US201213707301 申请日期 2012.12.06
申请人 KALRAY 发明人 COLLANGE Sylvain;BRUNIE Nicolas
分类号 G06F9/30 主分类号 G06F9/30
代理机构 代理人
主权项 1. A method for executing instructions on a single-program, multiple-data processor system having a fixed number of execution lanes, comprising: scheduling a primary instruction for execution with a first wave of multiple data; assigning the first wave to a corresponding primary subset of the execution lanes; scheduling a secondary instruction having a second wave of multiple data, such that the second wave fits in lanes that are unused by the primary subset of lanes; assigning the second wave to a corresponding secondary subset of the lanes; fetching the primary and secondary instructions; configuring the execution lanes such that the primary subset is responsive to the primary instruction and the secondary subset is simultaneously responsive to the secondary instruction; and simultaneously executing the primary and secondary instructions in the execution lanes.
地址 Orsay FR