发明名称 MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING
摘要 This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.
申请公布号 US2014164692(A1) 申请公布日期 2014.06.12
申请号 US201313769976 申请日期 2013.02.19
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 Franceschini Michele M.;Hunter Hillery C.;Jagmohan Ashish;Kilmer Charles A.;Kim Kyu-hyoun;Lastras-Montano Luis A.;Qureshi Moinuddin K.
分类号 G11C11/406 主分类号 G11C11/406
代理机构 代理人
主权项 1. A computer system comprising: a memory controller coupled to a processor and to a DRAM (dynamic random access memory); wherein the computer system is configured to determine the location of a weak cell in a DRAM row that can only hold one reliable logic state during a refresh interval; and wherein the memory controller is configured to: receive data from the processor,encode the data into a bit vector to be written to memory, wherein: for each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell; andthe bit vector is longer than the data.
地址 Armonk NY US