| 发明名称 |
MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME |
| 摘要 |
A memory controller connected with a storage medium via a plurality of channels is provided which includes a signal processing block including a plurality of signal processing engines; and a decoding scheduler configured to control a data path such that at least one activated signal processing engine of the plurality of signal processing engines is connected with the plurality of channels, respectively. |
| 申请公布号 |
US2014164673(A1) |
申请公布日期 |
2014.06.12 |
| 申请号 |
US201314102979 |
申请日期 |
2013.12.11 |
| 申请人 |
WOO Seonghoon;KIM Haksun;KWON Euihyeok;PARK Jaegeun |
发明人 |
WOO Seonghoon;KIM Haksun;KWON Euihyeok;PARK Jaegeun |
| 分类号 |
G06F13/16;G06F13/40;G11C7/10 |
主分类号 |
G06F13/16 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory controller which is connected with a storage medium via a plurality of channels, comprising:
a signal processing block including a plurality of signal processing engines; and a decoding scheduler configured to control a data path such that at least one activated signal processing engine of the plurality of signal processing engines is connected with the plurality of channels, respectively.
|
| 地址 |
Hwaseong-si KR |
