| 摘要 |
Disclosed is a data output circuit. The data output circuit according to one embodiment of the present invention includes a delay signal generating block which generates a rising delay signal and a falling delay signal by reflecting an impedance calibration result in response to an impedance control command, a reset signal, and a test signal, a first delay block which outputs a corrected rising clock by correcting a duty ratio of a rising clock according to the control of the rising delay signal, and a second delay block which outputs a corrected falling clock by correcting a duty ratio of a falling clock according to the control of the falling delay signal. |
