DEVICE IN COMPUTER SYSTEM

摘要

A device includes a PCH including a reset control pin and a disable control pin. A BIOS chip to control the PCH to send a low logic level from the reset control pin to the reset pin to reset a Ethernet controller. A timing adjusting circuit and the Ethernet controller. The Ethernet controller includes a rest pin and a disable pin, the rest pin is connected to the reset control pin via the timing adjusting circuit, and the disable pin is connected to the disable control pin via the timing adjusting circuit. The PCH sends a low logic level from the disable control pin to the disable pin to disable the Ethernet controller, and the timing adjusting circuit delays the low logic level, which makes the low logic level of the disable pin come later than the high logic level of the reset pin.

主权项

1. A device comprising:
a platform controller hub PCH comprising a reset control pin and a disable control pin; a basic input/output system BIOS chip, connected to the PCH, to control the PCH to send a low logic level from the reset control pin to the reset pin to reset a Ethernet controller during booting of the device; a timing adjusting circuit; and the Ethernet controller, comprising a rest pin and a disable pin, the rest pin connected to the reset control pin via the timing adjusting circuit, and the disable pin connected to the disable control pin via the timing adjusting circuit; wherein the PCH is further controlled to send a low logic level from the disable control pin to the disable pin to disable the Ethernet controller during booting of the device, and the timing adjusting circuit is configured to delay the low logic level, which makes the low logic level of the disable pin come later than the high logic level of the reset pin.