Circuit for Heartbeat Detection and Beat Timing Extraction

摘要

A circuit and method for long term electrocardiogram (ECG) monitoring is implemented with the goal of reducing power consumption, battery size, and consequently device size. In one embodiment, the integrated circuit includes an amplifier cell having a plurality of input terminals and an output terminal; a QRS amplifier cell in communication with the output of the amplifier cell; a baseline amplifier cell in communication with the output of the amplifier cell; a comparator cell having a first input terminal in communication with the output terminal of the QRS amplifier cell; and a VDC cell having an input in communication with the output of the baseline amplifier cell and an output in communication with the second input terminal of the comparator cell, wherein the comparator cell generates an output pulse in response to the output signal from the amplifier cell and the output signal from the baseline amplifier cell.

主权项

1. A heartbeat detection device comprising:
an amplifier cell having a plurality of input terminals and an output terminal; a QRS amplifier cell having an input terminal and an output terminal, the input terminal of the QRS amplifier cell in communication with the output terminal of the amplifier cell; a baseline amplifier cell having an input terminal and an output terminal, the input terminal of the baseline amplifier cell in communication with the output terminal of the amplifier cell; a comparator cell having a first input terminal and a second input terminal and an output terminal, the first input terminal of the comparator cell in communication with the output terminal of the QRS amplifier cell; and a VDC cell having a first terminal in communication with the output terminal of the baseline amplifier cell and a second terminal in communication with the second input terminal of the comparator cell, wherein the amplifier cell outputs an output signal on the output terminal of the amplifier cell in response to input signals input to the input terminals of the amplifier module, wherein the comparator cell generates an output pulse in response to the output signal from the QRS amplifier cell and the output signal from the VDC cell.