SUB-GATE DELAY ADJUSTMENT USING DIGITAL LOCKED-LOOP

摘要

A delay locked loop (DLL) includes a delay line that delays a clock signal to generate a delayed clock signal, a phase frequency detector (PFD) for detecting a phase and/or frequency difference between the clock signal and the delayed clock signal, and a charge pump having an adjustable bias current for converting the phase and/or frequency difference taking into account a bias current adjustment into a control voltage, in which the control voltage controls an amount of delay in the delayed clock signal.

主权项

1. A charge pump for converting at least one of: a phase and a frequency difference into a control voltage, the charge pump comprising:
a first current component coupled between a voltage supply and a first output node; a second current component coupled between the voltage supply and a second output node, a control node of the first current component being coupled to a control node of the second current component; a common mode feedback circuit including a first input coupled to the first output node, a second input coupled to the second output node, and an output coupled to the control nodes of the first and second current components; wherein a first bias current source supplies a first tunable bias current directly to the first output node and switchably supplies a first constant bias current to the first and second output nodes, and a second bias current source supplies a second tunable bias current directly to the first output node and switchably supplies a second constant bias current to the first and second output nodes.