| 摘要 |
<p>Cache management circuitry responds to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction. Such that a valid bit associated with each entry in the cache is set to invalid for the address translations, invalid entries being available for update and not forming part of any lookup in the cache. Alternatively, in response to identification of a transaction stall fault to set a stall indicator associated with all address translations in the cache that relate to the context of the faulting transaction. This allows a processor for processing a stream of instructions to use a hierarchical memory system having a cache, where the memory stores tables having virtual to physical address translations, to maintain access to translations for stalled operations, ready for a resume instruction, but invalidate entries where a transaction needs to be terminated.</p> |
