| 摘要 |
A reversible shift register comprises a group of n CDR flip-flops, first OR gate, first and second AND gates in each bit, combinatorial binary adder SM of uncompressed binary code units number, first DC1 and second DC2 decoders for transformation of bit code of units number to unitary code of units, second OR gate in each bit, except last one, third OR gate. At each register bit two-input firat and second AND gates are used, and inverting control inputs of first and second decoders are connected respectively to left and right compressing inputs. |
