Method for fabricating a MOS transistor with reduced channel length variation

摘要

According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

主权项

1. A method for fabricating a MOS transistor, said method comprising:
forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate; forming a self-aligned extension region under a second sidewall of said gate, said self-aligned extension region extending into said first well from a second well extending under said gate, said self-aligned extension region and said second well having a same conductivity type; forming a drain region spaced apart from said second sidewall of said gate.