发明名称 Display device for reducing parasitic capacitance with a dummy scan line
摘要 A display device, in at least one embodiment, includes: a gate driver including a plurality of shift register stages each provided so as to correspond to each row, the gate driver outputting a gate signal for turning on switching elements in the each row; and a source driver outputting a data signal in accordance with an image to be displayed. For a row (first row) located at an outermost position from which scanning by use of the gate signal starts, a dummy line is provided. The dummy line is driven by a gate start pulse inputted into a shift register in the first row.
申请公布号 US8749469(B2) 申请公布日期 2014.06.10
申请号 US20080734932 申请日期 2008.08.28
申请人 Sharp Kabushiki Kaisha 发明人 Iwamoto Akihisa;Morii Hideki;Mizunaga Takayuki;Hirokane Masahiro;Ohta Yuuki
分类号 G09G3/36 主分类号 G09G3/36
代理机构 代理人
主权项 1. A display device comprising: a display panel including: scanning signal lines;data signal lines;pixel electrodes; andswitching elements, each of the switching elements having (i) one terminal connected with one of the pixel electrodes and (ii) another terminal connected with one of the data signal lines,each of the scanning signal lines turning on/off switching elements corresponding thereto,the each scanning signal line forming one of rows together with the switching elements connected thereto, and pixel electrodes respectively connected to these switching elements; a scanning signal line driving circuit including a plurality of shift registers each provided so as to correspond to each of the rows, the scanning signal line driving circuit outputting a scanning signal for turning on the switching elements in the each row; a data signal line driving circuit outputting a data signal in accordance with an image to be displayed; a dummy scanning signal line provided for an outermost row located at an outermost position from which scanning by use of the scanning signal starts, the dummy scanning signal line being driven by a gate start pulse inputted into a shift register corresponding to the outermost row located at the outermost position, the gate start pulse driving the dummy scanning signal line has a voltage level allowing the switching element to be turned on/off,the gate start pulse driving the dummy scanning signal line is set at the voltage level by a buffer; and a control device generating the gate start pulse and a clock for driving the scanning signal line driving circuit, the control device including the buffer for generating the gate start pulse,the dummy scanning signal line is connected to a signal line connecting the control device with the scanning signal line driving circuit; andthe gate start pulse is inputted into the scanning signal line driving circuit and the dummy scanning signal line via the signal line.
地址 Osaka JP