发明名称 Semiconductor storage device
摘要 A memory includes a sense amplifier connected to one or more of bit lines and configured to sense data stored in the memory cells; and a word line driver configured to control a voltage of one or more of word lines. The memory cells constitute a memory block. The memory cells constitute a memory block being a unit of memory cells on which a data erasing operation is performed. A controller changes an erase condition during the data erasing operation performed on the memory block or a verify condition for a verify check of verifying whether the data has been erased from the memory cells in the memory block, in proportion to a ratio of number of predetermined logical value data to the data in the memory block or the page before the data erasing operation.
申请公布号 US8750052(B2) 申请公布日期 2014.06.10
申请号 US201213370701 申请日期 2012.02.10
申请人 Kabushiki Kaisha Toshiba 发明人 Aoki Satoshi;Hatakeyama Kazuo;Nakajima Yasushi
分类号 G11C16/04 主分类号 G11C16/04
代理机构 代理人
主权项 1. A semiconductor storage device comprising: a plurality of bit lines; a plurality of word lines crossing the bit lines; a plurality of memory cells respectively provided to correspond to intersections between the bit lines and the word lines; a sense amplifier connected to one or more of the bit lines and configured to sense data stored in the memory cells; and a word line driver configured to control voltages of one or more of the word lines, wherein a plurality of the memory cells constitute a memory block, the memory block being a unit of memory cells on which a data erasing operation is performed, and the memory cells commonly connected to each of the word lines constitute a page in the memory block, and the semiconductor storage device further comprises a control part configured to change an erase condition during the data erasing operation performed on the memory block or a verify condition for a verify check of verifying whether the data has been erased from the memory cells in the memory block, in proportion to a ratio of number of predetermined logical value data to the data in the memory block or the page before the data erasing operation.
地址 Tokyo JP