| 发明名称 |
Method and apparatus for a 1 MHz long training field design |
| 摘要 |
An approach is provided for defining a 1 MHz preamble of a packet. The approach involves determining a preamble sequence of a packet, the preamble sequence having a determinable length. The approach also involves causing, at least in part, the preamble sequence to be divided into a predetermined number of blocks. The approach further involves causing, at least in part, a mathematical operation and a summation over the predetermined number of blocks and a corresponding number of received blocks. The approach also involves causing, at least in part, the summation to be maximized to determine the preamble sequence corresponds to one of a first bandwidth or a second bandwidth, the second bandwidth being greater than the first bandwidth, to determine a type of the packet. |
| 申请公布号 |
US8750215(B2) |
申请公布日期 |
2014.06.10 |
| 申请号 |
US201213532056 |
申请日期 |
2012.06.25 |
| 申请人 |
Intel Corporation |
发明人 |
Azizi Shahrnaz;Kenney Thomas;Perahia Eldad |
| 分类号 |
H04W4/00;H04L27/26 |
主分类号 |
H04W4/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
determining a preamble sequence of a packet, the preamble sequence having a determinable length; causing, at least in part, the preamble sequence to be divided into a predetermined number of blocks; causing, at least in part, a mathematical operation and a summation over the predetermined number of blocks and a corresponding number of received blocks; and causing, at least in part, the summation to be maximized to determine the preamble sequence corresponds to one of a first bandwidth or a second bandwidth, the second bandwidth being greater than the first bandwidth, to determine a type of the packet.
|
| 地址 |
Santa Clara CA US |
