发明名称 |
Method of fabricating a gate |
摘要 |
A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer. |
申请公布号 |
US8748239(B2) |
申请公布日期 |
2014.06.10 |
申请号 |
US201313956482 |
申请日期 |
2013.08.01 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Kim Jong-Pil;Jang Young-Goan;Kim Dong-Won;Cho Hag-Ju |
分类号 |
H01L21/335;H01L21/8232 |
主分类号 |
H01L21/335 |
代理机构 |
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代理人 |
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主权项 |
1. A method of fabricating a gate, the method comprising:
forming a device isolation layer in a substrate, a top surface of the device isolation layer being higher than a top surface of the substrate; sequentially forming a first layer and a second layer on substantially an entirety of the substrate including the device isolation layer, the second layer having a stepped surface on the substrate, the stepped surface overlapping the device isolation layer; planarizing the second layer such that the stepped surface is removed; and forming a plurality of stacked structures spaced apart on the substrate, after planarizing the second layer by patterning the first layer and the second layer to form a plurality of patterned first layers and a plurality of patterned second layers, at least one of the plurality of patterned second layers being on the device isolation layer, a top surface of each of the plurality of patterned second layers being arranged at a same distance from the substrate.
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地址 |
Suwon-si, Gyeonggi-do KR |