Multi-phase clock generation apparatus and method

摘要

A multi-phase clock generator may receive an input clock signal as an input. The clock generator may also receive an inverse of the input clock signal. The clock generator may produce a plurality of output clock signals having different phases. The phases of the output clock signals may be evenly spaced. The output clock signals may have a similar waveform to the input clock signal, with a frequency that is lower than the input clock signal by a division factor.

主权项

1. A clock generation apparatus, comprising:
a plurality of stages arranged in a ring with an output terminal of each stage coupled to an input terminal of a next stage at an output node, each stage configured to receive complementary input clock signals at respective first and second clock terminals and to receive a prior output signal from a prior stage at the input terminal and produce an output signal at the output terminal that is an inverted and delayed version of the prior output signal, wherein individual stages are gated to pass an inverted version of the prior output signal from the prior stage as the output signal at the output terminal responsive to the complementary input clock signals; and a plurality of latch structures, each latch structure being configured to cause an output signal at a respective output node to be the inverse of another output signal at a respective other output node; wherein the output signals at each output node have different phases.