发明名称 TEST METHOD, TEST PROGRAM AND TEST CONTROL DEVICE
摘要 PROBLEM TO BE SOLVED: To efficiently detect the failure of a circuit for connecting a plurality of arithmetic units.SOLUTION: In this test method, it is possible to test a device having first to third arithmetic units. In this test method, a test instruction string including processing using a second circuit for connecting the second arithmetic unit to the third arithmetic unit is generated by using a processing instruction string as an instruction string including processing using a first circuit for connecting the first arithmetic unit to the second arithmetic unit. In this case, the test instruction string is generated by adding an additional instruction string as an instruction string which does not give any change to the arithmetic result of an instruction included in the processing instruction string to the leading of the processing instruction string. The presence/absence of the failure of the first circuit is determined by allowing the device to execute the test instruction string from the leading of the processing instruction string. Also, the presence/absence of the failure of the second circuit is detected by allowing the device to execute the test instruction string from the additional instruction string.
申请公布号 JP2014106928(A) 申请公布日期 2014.06.09
申请号 JP20120261729 申请日期 2012.11.29
申请人 FUJITSU LTD 发明人 NISHIMAKI SHIZUKA;TERANISHI SHINSUKE
分类号 G06F11/22 主分类号 G06F11/22
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