| 摘要 |
PROBLEM TO BE SOLVED: To increase a tolerance to surge voltage while keeping a low parasitic capacitance of a gate and maintaining high speed switching performance.SOLUTION: When an off driving signal turns a FET 5 off, a surge voltage occurs to bring a drain-source voltage VDS of the FET 5 to or above a protective voltage Vm1. Meanwhile, a detection voltage by a first voltage detection circuit 6A becomes higher than a threshold voltage Vth to turn a FET 13 off and a FET 14 on in a control circuit 9, which in turn turns a FET 11 off to bring a switch circuit 8 to a high impedance. A detection voltage by a second voltage detection circuit 6B later raises a gate voltage VGS of the FET 5 to or above a gate threshold voltage via a diode 15. The FET 5 then shoots through to release energy of the surge voltage to a source side. |
