EMULATED MESSAGE SIGNALED INTERRUPTS IN MULTIPROCESSOR SYSTEMS

摘要

A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache memories. A first cache memory associated a first of the execution cores includes a plurality of cache lines. The first cache memory has a cache controller including hardware logic, microcode, or both to identify a first cache line as an interrupt reserved cache line and map the first cache line to a selected memory address associated with an I/O device. The selected system address may be a portion of configuration data in persistent storage accessible to the processor. The controller may set a coherency state of the first cache line to shared and, in response to detecting an I/O transaction including I/O data from the I/O device and containing a reference to the selected memory address, emulate a first message signaled interrupt identifying the selected memory address.

主权项

1. A processor, comprising:
first storage to store configuration data indicating a memory address associated with an I/O device; and a first processing core; a first cache memory associated the first processing core, the first cache memory including:
a plurality of cache lines; anda cache controller to:
identify a first cache line as an interrupt reserved cache line;map the first cache line to the memory address;set a coherency state of the first cache line to shared; andemulate a first message signaled interrupt identifying the memory address responsive to detecting an I/O transaction includes I/O data from the I/O device and the I/O transaction includes a reference to the memory address.