发明名称 LOW-POWER ENCRYPTION APPARATUS AND METHOD
摘要 A low-power encryption apparatus and method are provided. The low-power encryption apparatus includes a mask value generation unit, a mask value application unit, a round key application unit, a mask operation unit, a shift operation unit, and a shift operation correction unit. The mask value generation unit generates a mask value M having the same bit length as input round function values. The mask value application unit generates first masking round function values by applying the mask value M. The round key application unit generates second masking round function values by applying round key values. The mask operation unit generates third masking round function values by performing a mask addition operation. The shill operation unit generates fourth masking round function values by performing a circular shift operation. The shift operation correction unit generates output round function values by performing an operation using the mask value M.
申请公布号 US2014153725(A1) 申请公布日期 2014.06.05
申请号 US201313930860 申请日期 2013.06.28
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 KANG Jun-Ki;LEE Sang-Han;LEE Bong-Soo;RYU Seok;AHN Jung-Chul;PARK Jung-Gil
分类号 H04L9/06 主分类号 H04L9/06
代理机构 代理人
主权项 1. A low-power encryption apparatus comprising: a mask value generation unit configured to generate a mask value M having a bit length identical to that of input round function values; a mask value application unit configured to generate first masking round function values by applying the mask value M to each of the input round function values; a round key application unit configured to generate second masking round function values by applying round key values to the first round function values; a mask operation unit configured to generate third masking round function values by performing a mask addition operation on the second masking round function values; a shift operation unit configured to generate fourth masking round function values by performing a circular shift operation on the third masking round function values; and a shift operation correction unit configured to generate output round function values by performing an operation using the mask value M on the fourth masking round function values.
地址 Daejeon KR