发明名称 SYSTEMS AND METHODS FOR ENCODING AND DECODING OF CHECK-IRREGULAR NON-SYSTEMATIC IRA CODES
摘要 Systems and methods for encoding and decoding check-irregular non-systematic IRA codes of messages in any communication or electronic system where capacity achieving coding is desired. According to these systems and methods, IRA coding strategies, including ones that employ capacity-approaching non-systematic IRA codes that are irregular and that exhibit a low error floor, are employed. These non-systematic IRA codes are particularly advantageous in scenarios in which up to half of coded bits could be lost due to channel impairments and/or where complementary coded bits are desired to transmit over two or more communications sub-channels. An encoder includes information bit repeaters and encoders, one or more interleavers, check node combiners, a check node by-pass and an accumulator. A decoder includes a demapper, one or more check node processors, an accumulator decoder, a bit decoder, and one or more interleavers/deinterleavers.
申请公布号 US2014157092(A1) 申请公布日期 2014.06.05
申请号 US201314052440 申请日期 2013.10.11
申请人 DIGITAL POWERRADIO, LLC 发明人 Vojcic Branimir R.;Papaharalabos Stylianos
分类号 H04L1/00 主分类号 H04L1/00
代理机构 代理人
主权项 1. A system for encoding check-irregular non-systematic irregular repeat accumulate codes, the system comprising: a. a plurality of information bit repeaters having a degree N, where degree N produces N identical replicas of an information bit, said plurality of bit repeaters produce a first set of coded bits; b. an interleaver that interleaves said first set of coded bits; c. two or more sets of check node combiners of different degrees, each degree being greater than or equal to 2, wherein a check node combiner of degree M produces a second set of coded bits from said interleaved first set of coded bits, wherein at least one of said check node combiners includes one or more modulo-2 adders; d. an encoder; and e. a check node by-pass that passes said first set of coded bits to the encoder, bypassing the two or more sets of check node combiners, as a second set of coded bits, wherein the encoder encodes the second set of coded bits from the check node combiners and from the check node bypass.
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