METHOD AND SYSTEM FOR PROVIDING A SMART MEMORY ARCHITECTURE

摘要

A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The system may include a smart memory controller capable of performing a bit error rate built-in self test. The smart memory control may include bit error rate controller logic configured to control the bit error rate built-in self test. A write error rate test pattern generator may generate a write error test pattern for the bit error rate built-in self test. A read error rate test pattern generator may generate a read error test pattern for the built-in self test. The smart memory controller may internally generate an error rate timing pattern, perform built-in self test, measure the resulting error rate, automatically adjust one or more test parameters based on the measured error rate, and repeat the built-in self test using the adjusted parameters.

主权项

1. A method for providing a bit error rate built-in self test on a memory device, the method comprising:
entering a test mode; internally generating, by the memory device, an error rate timing pattern; performing, by the memory device, the bit error rate built-in self test based on the internally generated error rate timing pattern; measuring an error rate resulting from the bit error rate built-in self test; and repeating the bit error rate built-in self test.