METHODS AND APPARATUSES FOR MEMORY TESTING WITH DATA COMPRESSION

摘要

Apparatuses and methods for memory testing with data compression is described. An example apparatus includes a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory. Each of the latch test circuits is configured to receive test data and is configured to latch data from the corresponding global data line or a corresponding mask bit. Each of the plurality of latch test circuits is further configured to output data based at least in part on the corresponding mask bit. A comparison circuit is coupled to an output of each of the latch test circuits and is configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicative of whether all the output data matches.

主权项

1. An apparatus, comprising:
a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory, wherein each of the latch test circuits is configured to receive test data and configured to latch data from the corresponding global data line, and configured to latch a corresponding mask bit, each of the plurality of latch test circuits further configured to output data based on the corresponding mask bit; and a comparison circuit coupled to an output of each of the latch test circuits and configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicating whether the output data matches.