MEMORY SUBSYSTEM DATA BUS STRESS TESTING

摘要

A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.

主权项

1. A memory subsystem comprising:
a memory device to store data and execute memory device commands to access and manage the data; a memory controller coupled to the memory device via a data bus, to receive a test transaction, the test transaction indicating one or more memory I/O (input/output) operations to perform a test on a memory device coupled to the memory controller; a test signal generator of the memory controller to generate a test data signal pattern in response to the memory controller receiving the test data transaction, the test signal generator including multiple different pattern signal generators to generate different types of signal patterns; and a scheduler of the memory controller to schedule the test data signal pattern in accordance with a memory device I/O protocol, and sending the test data signal pattern to the memory device to cause the memory device to execute an I/O operation to implement a portion of the test transaction.