| 摘要 |
Disclosed is a multi-10-gigabit interface device designed based on 1U. The device is designed based on multi-core MIPS architecture, and includes the modules: a multi-core processor processing module for processing parallel synchronous operation among 12 cores, each core being capable of reaching 64-bit computation ability; a switch chip processing module for providing a 240G access capability index and providing a combination of 16 10-gigabit SFP + interfaces + 8 gigabit Combo interfaces under a 1U height, having great advantages in interface density and throughput capability; and a heat dissipation optimization processing module for heat dissipation of important chips of a PCB and a power supply in a whole system, reducing the power consumption.The present invention can excellently solve the problem that existing data acquisition is not flexible, not only occupies the space of a carrier, but also increases the project cost, and completely meets field link collection in a form of 16 10-gigabits + 8 gigabits. |
