发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AUTOMATIC LAYOUT DESIGN SYSTEM, AUTOMATIC LAYOUT DESIGN METHOD, AND PROGRAM
摘要 <p>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit automatic layout design system, automatic layout design method, and program, which allow automatic arrangement and automatic wiring of components.SOLUTION: A semiconductor integrated circuit layout design device 50 includes: a layout information reception unit 511 that receives as initial arrangements a layout outline, component graphics and coordinates, and terminal coordinates; a signal wiring region division unit 512 that extracts a wiring region that is in an area other than a component arrangement region and where signal wiring is allowed; a wiring path creation unit 513 that creates wiring paths that pass through the wiring region and connect corresponding terminals to each other; a passing signal wiring calculation unit 514 that identifies the wiring paths that go in and out of the wiring region, and calculates the number of wiring paths that pass the wiring region on the basis of an identification result; and a wiring region optimization unit 515 that optimizes the width of the wiring region according to the number of wiring paths.</p>
申请公布号 JP2014102579(A) 申请公布日期 2014.06.05
申请号 JP20120252584 申请日期 2012.11.16
申请人 RENESAS ELECTRONICS CORP 发明人 MURATA KENTARO
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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