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1. An on-chip processing system comprising:
a memory bank configured to store packets of information, wherein an individual packet includes a packet header and a packet payload, wherein the packet header includes one or more operator codes; an interconnect module configured to receive packets from individual ones of a set of interconnect sources, wherein the set of interconnect sources includes a controller and the memory bank, wherein the interconnect module is further configured to transfer packets to individual ones of a set of interconnect destinations, wherein the set of interconnect destinations includes the controller and an external device, wherein transfer of individual packets is guided by one or more operator codes therein; the controller configured to receive packets from the interconnect module and further configured to transfer packets to individual ones of a set of controller destinations, wherein the set of controller destinations includes a first processing engine, a second processing engine, and the interconnect module, and wherein transfer of individual packets is guided by one or more operator codes therein; and multiple processing engines including the first processing engine and the second processing engine, wherein an individual one of the multiple processing engines is configured to generate, responsive to receiving one or more packets from the controller, output packets by processing the one or more received packets, wherein individual ones of the generated output packets include an output packet header, the output packet header including one or more operator codes, wherein the controller is further configured to receive the output packets from individual ones of the processing engines, and wherein the controller is further configured to transfer the output packets, based on one or more operator codes therein, to individual ones of the set of controller destinations.
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