发明名称 |
APPARATUS, METHOD AND SYSTEM FOR PROVIDING TERMINATION FOR MULTIPLE CHIPS OF AN INTEGRATED CIRCUIT PACKAGE |
摘要 |
Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series |
申请公布号 |
WO2014085267(A1) |
申请公布日期 |
2014.06.05 |
申请号 |
WO2013US71533 |
申请日期 |
2013.11.22 |
申请人 |
INTEL CORPORATION;VERGIS, GEORGE;BAINS, KULJIT S.;MCCALL, JAMES A.;CHANG, GE |
发明人 |
VERGIS, GEORGE;BAINS, KULJIT S.;MCCALL, JAMES A.;CHANG, GE |
分类号 |
G11C11/40 |
主分类号 |
G11C11/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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