3D FLOORPLANNING USING 2D AND 3D BLOCKS

摘要

The disclosed embodiments are directed to systems and methods (100) for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies. The disclosed embodiments provide better floorplan solutions that further minimize wirelength and improve the overall power/performance envelope of the designs. The disclosed methodology may be used to construct new 3D IP blocks (10) to be used in designs that are built using monolithic 3D integration technology.