| 摘要 |
If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit (12) includes a delay circuit (DL) to delay input data that is input in parallel to a data input terminal of a second flip-flop (FF1) provided in a subsequent stage of a first flip-flop (FF0), a third flip-flop (FFT) that receives output of the delay circuit (DL), and a comparator (CMP) that compares output of the second flip-flop (FF1) and output of the third flip-flop (FFT). First test data (tv1) and second test data (tv2) are input to the malfunction pre-detecting circuit (12) in an operation test mode for testing operation of the malfunction pre-detecting circuit (12). The test data (tv2) is input to the delay circuit (DL). The comparator (CMP) compares the test data (tv1) and output of the flip-flop (FFT) in the operation test mode. |
