发明名称 Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique
摘要 A thermally-grown oxygen-containing gate dielectric and select gate are formed in an NVM region. A high-k gate dielectric, barrier layer, and dummy gate are formed in a logic region. The barrier layer may include a work-function-setting material. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, resulting in an opening. A gate layer is formed over the charge storage layer in the NVM region and within the opening in the logic region, wherein the gate layer within the opening together with the barrier layer form a logic gate in the logic region, and the gate layer is patterned to form a control gate in the NVM region.
申请公布号 US8741719(B1) 申请公布日期 2014.06.03
申请号 US201313790014 申请日期 2013.03.08
申请人 Freescale Semiconductor, Inc. 发明人 Hall Mark D.;Baker, Jr. Frank K.;Shroff Mehul D.
分类号 H01L21/8247 主分类号 H01L21/8247
代理机构 代理人
主权项 1. A method for forming a semiconductor device having a non-volatile memory (NVM) region and a logic region, the method comprising: forming a thermally grown oxygen-containing gate dielectric over a semiconductor layer and a select gate over the thermally grown oxygen-containing gate dielectric in the NVM region while protecting the logic region; forming a high-k gate dielectric over the semiconductor layer, a barrier layer over the high-k gate dielectric, and a dummy gate over the barrier layer in the logic region, while protecting the NVM region; forming a first dielectric layer over the semiconductor layer in the NVM region and the logic region, wherein the first dielectric layer surrounds the select gate and thermally grown oxygen-containing gate dielectric in the NVM region and surrounds the dummy gate, the barrier layer, and the high-k gate dielectric in the logic region; removing the first dielectric layer from the NVM region while protecting the first dielectric layer in the logic region; forming a charge storage layer over the semiconductor layer and select gate in the NVM region, and over the first dielectric layer and dummy gate in the logic region; removing the charge storage layer from the logic region; removing the dummy gate in the logic region which results in an opening in the logic region; forming a gate layer over the charge storage layer in the NVM region and over the first dielectric layer and in the opening in the logic region; removing a top portion of the gate layer in the NVM region and the logic region, wherein a remaining portion of the gate layer in the opening and the barrier layer together form a logic gate in the logic region; and patterning a remaining portion of the gate layer in the NVM region to form a control gate in the NVM region that is laterally adjacent the select gate, wherein a top surface of the control gate is substantially coplanar with a top surface of the logic gate.
地址 Austin TX US