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1. A display device comprising:
a pixel array unit formed by arranging pixels in a form of a matrix, said pixels including an electrooptic element, a writing transistor which writes a video signal, a retaining capacitance which retains said video signal written by said writing transistor, and a drive transistor which drives said electrooptic element on a basis of said video signal retained in said retaining capacitance; a first scanning circuit configured to selectively supply a first potential and a second potential lower than said first potential to a power supply line that is disposed in each pixel row of said pixel array unit, said power supply line supplying current through said drive transistor to said electrooptic element; a second scanning circuit configured to set said writing transistor in a conducting state or a non-conducting state while selecting the pixels of said pixel array unit in row units by driving said writing transistor in each pixel row of said pixel array unit, wherein said writing transistor is switched from said non-conducting state to said conducting state at a first timing occurring when said second potential is being supplied to said power supply line, and a selecting circuit configured to selectively supply (1) said video signal, (2) a first offset voltage serving as a reference for said video signal and being different from said video signal, and (3) a second offset voltage different from said first offset voltage and different from said video signal to a signal line disposed in each column of said pixel array unit, and configured to:
supply said second offset voltage to the signal line at least during a second timing occurring after the first timing and when said writing transistor is in said conducting state while said second potential is supplied to said power supply line, wherein the second potential changes to said first potential in said power supply line at a third timing occurring after the second timing;supply said first offset voltage to the signal line in place of said second offset voltage after the third timing and before a fourth timing, wherein said writing transistor is switched from said conducting state to said non-conducting state at the fourth timing, andsupply said video signal to the signal line in place of said first offset voltage after said fourth timing.
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