| 摘要 |
A field-effect transistor involves a drain electrode, a drift region, a body region, a source region, a gate insulator layer, and a gate electrode. The drift region is disposed above the drain electrode. The body region extends down into the drift region from a first upper semiconductor surface. The source region is ladder-shaped and extends down in the body region from a second upper semiconductor surface. The first and second upper semiconductor surfaces are substantially planar and are not coplanar. A first portion of the body region is surrounded laterally by a second portion of the body region. The second portion of the body region and the drift region meet at a body-to-drift boundary. The body-to-drift boundary has a central portion that is non-planar. A gate insulator layer is disposed over the source region and a gate electrode is disposed over the gate insulator. |
| 主权项 |
1. A device comprising:
a drain electrode; a drift region disposed above the drain electrode; a body region that extends down into the drift region from a first upper semiconductor surface; a source region that extends down into the body region from a second upper semiconductor surface, wherein the first upper semiconductor surface is substantially planar, wherein the second upper semiconductor surface is substantially planar, wherein the first and second upper semiconductor surfaces are not coplanar, wherein a first portion of the body region is disposed at least in part under the source region, wherein the first portion of the body region is surrounded laterally by a second portion of the body region, wherein the second portion of the body region and the drift region meet at a body-to-drift boundary, wherein the body-to-drift boundary has a central portion, wherein the central portion of the body-to-drift boundary is directly beneath the first upper semiconductor surface, and wherein the central portion of the body-to-drift boundary is non-planar; a gate insulator layer disposed over the source region; and a gate electrode disposed over the gate insulator layer.
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